Itanium 2 processor For more details on the technical architecture, not chip implementations, see IA-64. Itanium aɪˈteɪniəm/ eye- TAY-nee-əm) is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel markets the processors for enterprise servers and high-performance computing systems. The Itanium architecture originated at Hewlett- Packard ( HP and was later jointly developed by HP and Intel. Itanium-based systems have been produced by HP (the HP Integrity Servers line) and several other manufacturers. As of 2008[update], Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power Architecture, and SPARC.[1] The most recent processor, Poulson was released on November 8, 2012. Contents 1 Market reception 1.1 High-end server market 1.2 Other markets 2 History 2.1 Development: 1989–2000 2.2 Itanium ( Merced 2001 2.3 Itanium 2: 2002–2010 2. ( Tukwila 2010 2. ( Poulson 2012 3 Market share 4 Hardware support 4.1 Systems 4.2 Chipsets 5 Software support 5.1 Emulation 6 Competition 7 Supercomputers and high-performance computing 8 Processors 8.1 Released processors 8.2 Future processors Kittson 9 Timeline 10 See also 11 References 12 External links Market reception[edit] High-end server market[edit] HP zx6000 system board with dual Itanium 2 processors Itanium 2 in 2003 When first released in 2001, Itanium's performance was disappointing compared to better-established RISC and CISC processors.[2][3] Emulation to run existing x86 applications and operating systems was particularly poor, with one benchmark in 2001 reporting that it was equivalent at best to a 100 MHz Pentium in this mode (1.1 GHz Pentiums were on the market at that time).[4] Itanium failed to make significant inroads against IA-32 or RISC, and suffered.
2 processor, code named Montecito, is the fourth generation of the Itanium 2 processor. Montecito builds on the strength of the previous Itanium 2 processors while bringing many new key technologies for performance and management to the Itanium processor family. Key improvements include multiple cores, multiple threads, cache hierarchy, and speculation with the addition of new instructions. This document describes key Montecito features and how Montecito differs in its implementation of the Itanium architecture from previous Itanium 2 processors. Some of this information may not be directly applicable to performance tuning, but is certainly needed to better understand and interpret changes in application behavior on Montecito versus other Itanium architecture-based processors. Unless otherwise stated, all of the restrictions, rules, sizes, and capacities described in this document apply specifically to Montecito and may not apply to other Itanium architecture-based processors. This document assumes a familiarity with the previous Itanium 2 processors and some of the unique properties and behaviors of those. Furthermore, only differences as they relate to performance will be included here. Information about Montecito features such as error protection, Virtualization Technology, Hyper- Threading Technology, and lockstep support may be obtained in separate documents. General understanding of processor components and explicit familiarity with Itanium processor instructions are assumed. This document is not intended to be used as an architectural reference for the Itanium architecture. For more information on the Itanium architecture, consult the Intel® Itanium® Architecture Software Developer’s Manual. Read the full Dual- Core Intel® Itanium® 2 Processor Reference Manual Update.
For the most updates, errata, and the latest information on Intel( R) processors, explore the resources available at The following sections describe processor manuals for Intel( R) 64, IA-32 architecture processors and for Intel( R) Itanium( R) processors. Intel( R) 64 and IA-32 Intel Architecture Manuals The Intel( R) 64 and IA-32 Intel Architectures Software Developer's Manual consists of the following volumes that describe the architecture and programming environment of all Intel( R) 64 and IA-32 Intel( R) Architecture processors. Volumes 1 and 2 are aimed at application programmers who are writing programs to run under existing operating systems or executives. Volume 1: Basic Architecture, describes the architecture and programming environment of processors supporting IA-32 and Intel( R) 64 Architectures. Volume 2 A: Instruction Set Reference, A- M describes the format of the instruction and provides reference pages for instructions (from A to M). Volume 2 B: Instruction Set Reference, N- Z provides reference pages for instructions (from N to Z). VMX instructions are treated in a separate chapter. Volume 3 A: System Programming Guide describes the operating-system support environment of an IA-32 and Intel( R) 64 architectures, including: memory management, protection, task management, interrupt and exception handling, multi-processor support, and thermal and power management features. Volume 3 B: System Programming Guide continues the coverage on system programming subjects begun in Volume 3 A. Volume 3 B covers debugging, performance monitoring, system management mode, and Intel( R) Virtualization Technology. Please refer to all five volumes when evaluating your design needs. The Intel( R) Pentium( R) 4 and Intel( R) Xeon( R) Processor Optimization Reference Manual, provides information on Intel Net Burst( R) microarchitecture, and describes code.
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